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Table 24. Coast Input Polarity Override Settings
10
2 Red Clamp Select
Override
0
1
0F
Result
Determined by chip (power-up default)
Determined by user
3 Coast Input Polarity
This bit indicates the polarity of the Coast signal that
is applied to the PLL COAST input.
This bit determines whether the red channel is
clamped to ground or to midscale. For RGB video, all
three channels are referenced to ground. For YCbCr
(or YUV), the Y channel is referenced to ground, but
the CbCr channels are referenced to midscale.
Clamping to midscale actually clamps to Pin 37.
Table 25. Coast Input Polarity Settings
Table 28. Red Clamp Select Settings
Coast Polarity
0
1
Result
Active low
Active high (power-up default)
Clamp
0
1
Result
Clamp to ground (power-up default)
Clamp to midscale (Pin 37)
Active low means that the clock generator ignores
10
1 Green Clamp Select
Hsync inputs when Coast is low, and continues
operating at the same nominal frequency until Coast
goes high.
This bit determines whether the green channel is
clamped to ground or to midscale.
Table 29. Green Clamp Select Settings
Active High means that the clock generator ignores
Hsync inputs when Coast is high, and continues
operating at the same nominal frequency until Coast
goes low.
Clamp
0
1
10
Result
Clamp to ground (power-up default)
Clamp to midscale (Pin 37)
0 Blue Clamp Select
This function needs to be used along with the Coast
polarity override bit (Bit 4).
This bit determines whether the blue channel is
clamped to ground or to midscale.
Table 30. Blue Clamp Select Settings
0F
2 Seek Mode Override
This bit is used to either allow or disallow the low
power mode. The low power mode (seek mode)
occurs when there are no signals on any of the Sync
inputs.
Clamp
0
1
11
Result
Clamp to ground (power-up default)
Clamp to midscale (Pin 37)
7–0 Sync Separator Threshold
This register is used to set the responsiveness of the
Table 26. Seek Mode Override Settings
sync separator. It sets the number of internal 5 MHz
Override
1
0
0F
Result
Allow seek mode (power-up default)
Disallow seek mode
1 PWRDN
This bit is used to put the chip in full power-down. See
the Power Management section for details on which
blocks are powered down.
clock periods the sync separator must count to before
toggling high or low. It works like a low-pass filter to
ignore Hsync pulses in order to extract the Vsync
signal. This register should be set to some number
greater than the maximum Hsync pulse width. The
sync separator threshold uses an internal dedicated
clock with a frequency of approximately 5 MHz.
Table 27. Power-Down Settings
The default for this register is 32.
Power-Down
Result
12
7–0 Pre-Coast
0
1
10
Power-down
Normal operation
7-3 Sync-on-Green Slicer Threshold
This register allows the comparator threshold of the
sync-on-green slicer to be adjusted. This register
This register allows the Coast signal to be applied
prior to the Vsync signal. This is necessary in cases
where pre-equalization pulses are present. The step
size for this control is one Hsync period.
The default is 0.
adjusts it in steps of 10 mV, with the minimum setting
equaling 10 mV (11111) and the maximum setting
equaling 330 mV (00000).
The default setting is 23, which corresponds to a
threshold value of 100 mV; for a threshold of 150 mV,
the setting should be 18.
13
7–0 Post-Coast
This register allows the Coast signal to be applied
following the Vsync signal. This is necessary when
post-equalization pulses are present. The step size for
this control is one Hsync period.
The default is 0.
Rev. 0 | Page 23 of 32
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